The present invention relates to a method for producing a nonvolatile semiconductor memory device. More specifically, the invention relates to a method for producing a non-volatile semiconductor memory device in which trenches in a memory cell region and trenches in other regions having a depth different from the depth of the trench in the memory cell region are formed in a reduced number of processes.
Large-scale integration of a semiconductor device that uses a silicon substrate is realized by providing a device isolating region between a plurality of transistors. As the device isolating regions used in the semiconductor device, there are a P-N junction isolating region, a LOCOS (local Oxidation of Silicon)-type field insulating film, and a trench isolating region. P-N junction isolating regions and trench isolating regions become device isolating regions for such devices as those in a collector region of a bipolar transistor having a deep P-N junction. The field insulating film, on the other hand, becomes a device isolating region between devices formed on the silicon substrate and wires provided on the silicon substrate, or a device isolating region for such devices as those in a source/drain regions of a MOS transistor having a shallow P-N junction.
The field insulating film has been employed for a device isolating region for a semiconductor device that comprises MOS transistors, and the field insulating film and either one of the P-N junction isolating region and the trench isolating region have been employed as a device isolating region for a semiconductor device that comprises bipolar transistors. With a progress of device miniaturization, special emphasis is placed on a self-alignment technique, and reduced size of a device isolating region are also pursued. Thus, in the semiconductor device that comprises the MOS transistors, an LOCOS-type field insulating film has become mainstream, while in the semiconductor device that comprises bipolar transistors, a combined use of the LOCOS-type field insulating film and the trench isolating region has become mainstream.
In the semiconductor device that comprises the MOS transistors, P-channel MOS transistors were mainly used at first. However, N-channel MOS transistors came into use, and now CMOS transistors have been mainly used. In a semiconductor device comprising the CMOS transistors, either one of an N well or a P well was employed. Recently, both N and P wells, that is, twin wells are employed. For this reason, even in the semiconductor device that comprises MOS transistors, a device isolating region for N and P wells having the deep P-N junction becomes necessary. In addition, use of a trench isolating region has begun to be studied as a measure against latch-up. Further, a BiCMOS transistor that comprises a CMOS transistor and a bipolar transistor has been spotlighted, so that the importance of the device isolating region that comprises a LOCOS-type field oxide film and a trench isolating region has increased.
Next, device isolating structures in a conventional non-volatile semiconductor device will be described with reference to a drawing. Referring to FIG. 18d, the non-volatile semiconductor device comprises a memory cell region 20, a device isolating region 21, and a peripheral circuit region 22. In the memory cell region 20, there is provided between cells device a device isolator 8a filled into a trench that penetrates through a first silicon oxide film 3 and extends into a silicon substrate 1. In the device isolating region 21, there is provided a field oxide film 2 formed on the surface of the silicon substrate 1 by a LOCOS process and a device isolator 8b filled into a trench that penetrates through the field oxide film 2 and extends into the silicon substrate 1. In the peripheral circuit region 22, there is provided between transistors a device isolator 8c which has been filled into a trench that penetrates through the first silicon oxide film 3 and extends into the silicon substrate 1. Generally, a silicon oxide film is employed for the device isolators 8a, 8b and 8c. 
A conventional typical method for producing the device isolators will be described.
The field oxide film 2 and the first silicon oxide film 3 that becomes a first gate insulating film are formed on the silicon substrate 1 by the LOCOS and thermal oxidation processes. Then, a silicon nitride film 6 is formed on the field oxide film 2 and the first silicon oxide film 3. Thereafter, a resist 7 for forming trenches in the respective regions is formed (see FIG. 18a).
Next, in the respective regions, the trenches having the same depth from an interface between the silicon substrate 1 and the field oxide film 2 and from an interface between the silicon substrate 1 and the first silicon oxide film 3 are formed (see FIG. 18b).
Then, after removing the resist 7, the trenches are filled with insulating films such as a silicon oxide film. The device isolators 8a, 8b and 8c are thereby formed.
Then, the silicon oxide film 3 is removed from the peripheral circuit region 22 to form a p-well 30, and then a gate insulation film 32 is selectively formed on the surface of the peripheral circuit region 22. Thereafter, floating gates 4 are formed on the memory cell region (see FIG. 18c).
Next, an ONO film 9 is selectively formed on the floating gates 4, and then control gates 10a are formed on the memory cell region, and gates 10b and 10c are formed on the peripheral circuit region.
An N-type diffusion layer 31 that becomes source/drain regions are formed with respect to the gates 10b and 10c on the peripheral circuit region (see FIG. 18d). With this arrangement, a source/drain region associated with the gate 10b and a source/drain region associated with the gate 10c are isolated by the device isolator 8c. 
Forming of trenches in the respective regions with the same depth from the interface between the silicon substrate 1 and the field oxide film 2 and from the interface between the silicon substrate 1 and the first silicon oxide film 3 in the above-mentioned way, results in the following problems.
The device isolators 8a that achieve isolation between memory devices on the memory cell region 20 and the device isolator 8c that achieves isolation between source/drain regions for adjacent transistors on the peripheral circuit region 22 have optimum depths, respectively. Since an impurity diffusion region that becomes source wiring is formed under the trenches filled with the device isolators 8a, the depth of the device isolator 8a cannot be made to be so deep.
On the other hand, if the depth of the device isolator 8c is shallow, a parasitic bipolar transistor is formed between the source and the drain of adjacent transistors, so that so-called latch-up may occur. Thus, the depth of the device isolator 8c cannot be made to be so shallow.
In other words, if the depth of the source/drain regions for the transistors become close to the depth of the device isolator 8c, the parasitic effects of an npn bipolar transistor arise, where a source/drain region 31 between the adjacent transistors is made to be an emitter and a collector, and the p-well 30 is made to be a base. Thus, it is necessary for the device isolator 8c to have a depth just sufficient for ensuring isolation of the source/drain regions 31.
In short, if the depth of the device isolator 8c is adjusted to the depth required for the device isolators 8a, latch-up might occur in the peripheral circuit region 22.
On the contrary, if the depth of the device isolators 8a is adjusted to the depth required for the device isolator 8c, formation of source wiring under the trenches filled with the device isolators 8a becomes difficult.
In order to solve the problems described above, separate formation of trenches in the respective regions can be conceived. However, if the separate formation is performed, number of the photo-lithography processes increases, thereby leading to a rise in cost.
In such a publication as JP Patent Kokai JP-A-01-309373, a technique for forming trenches having different depths in a single process is described. In this technique, a silicon oxide film having a desired thickness is formed in advance on a region where shallow trenches are to be formed. Then, utilizing an etching rate difference between the silicon oxide film and silicon, trenches having different depths can be formed.
However, for formation of the silicon oxide film in advance, a dedicated photo-lithography process is required. Thus, though a reduction in the number of processes to a certain extent is achieved in view of the number of the processes required for filling the trenches, a substantial reduction in lithography processes cannot be brought about.
On the contrary, the number of the lithography processes increases. Further, in order to form trenches having different depths, a layer or a silicon oxide film for adjusting the depths of the trenches, which will be removed in the future, must be formed. Therefore it takes much more time to perform all of the manufacturing processes.
In JP Patent Kokai JP-A-10-107167, a technique for fabricating cell arrays isolated by trenches is described. In this technique, a tunnel oxide film, floating gates, a silicon oxide film, and a silicon nitride film are deposited on a substrate in this order.
Then, the silicon nitride film, silicon oxide film, floating gates, tunnel oxide film, and silicon substrate are etched in a stripe form continuously in this order. Then, after the silicon oxide film is filled into the trenches, grinding or planarization is performed by using a CMP technique until the silicon nitride film is exposed.
Thereafter, the silicon nitride film and the silicon oxide film on the floating gate are removed. By patterning in the channel width direction in this way, the width of a channel and the width of a floating gate are determined in a self-alignment manner.
However, when a memory is formed, or when the widths of the channel and the floating gate are determined by the self-alignment technique, device isolation in the peripheral circuit region other than the memory cell region had to be performed in a separate process, by trench isolation or LOCOS isolation. For this reason, it takes much time to perform all of the manufacturing processes, thereby increasing the cost of manufacturing.
Especially when a device isolator corresponding to the device isolator 8c in FIG. 18 is to be employed in commonly used transistors on the peripheral circuit region for miniaturization, the number of the processes is further increased.
The present invention has been made to overcome the problems described above.
Accordingly, it is an object of the present invention to provide a method for producing a non-volatile semiconductor memory device in which trenches having different depths can be formed in a reduced number of processes.
The above object and other objects of the invention are satisfied, at least in part, in accordance with one aspect of the present invention, by providing a method for producing a non-volatile semiconductor memory device having a memory cell region and a peripheral circuit region, said memory cell region including a plurality of memory cells each comprising a floating-gate transistor, said peripheral circuit region including at least a transistor circuit in a periphery of said memory cell region, said method comprising:
a first step of forming a gate insulation film on a semiconductor substrate;
a second step of forming a floating gate film on said gate insulation film and then selectively etching said floating gate film on said peripheral circuit region;
a third step of forming an etching mask having at least a first opening and a second opening respectively over said floating gate film and said gate insulation film, said first opening being provided to expose a part of said floating gate film on said memory cell region, said second opening being provided to expose a part of said gate insulation film on said peripheral circuit region;
a fourth step of selectively etching said gate insulation film until said semiconductor substrate is exposed from said second opening;
a fifth step of etching said floating gate film exposed from said first opening and said gate insulation film under said floating gate film, and etching said semiconductor substrate exposed from said second opening simultaneously, until said semiconductor substrate is exposed from said first opening;
a sixth step of simultaneously etching said semiconductor substrate exposed respectively from said first opening and said second opening; and
a seventh step of removing said etching mask and then filling respective trenches formed by said sixth step of etching with an insulating material.
In accordance with a second aspect of the present invention, there is provided a method for producing a non-volatile semiconductor memory device having a memory cell region, a peripheral circuit region, and a device isolating region on a semiconductor substrate, said memory cell region having a plurality of memory cells each comprising a floating-gate transistor, said peripheral circuit region including at least a transistor circuit in a periphery of said memory cell region, said device isolating region for isolating devices on said memory cell region from devices on said peripheral circuit region, said method comprising:
a first step of forming a field insulating film on said device isolating region and then forming a gate insulation film on said memory cell region and said peripheral circuit region;
a second step of forming a floating gate film on said gate insulation film and then selectively etching said floating gate film on said peripheral circuit region;
a third step of forming an etching mask having at least a first opening and a third opening, said first opening being provided to expose a part of said floating gate film on said memory cell region, said third opening being provided to expose a part of said field insulating film on said device isolating region;
a fourth step of selectively etching said field insulating film exposed from said third opening until said semiconductor substrate is exposed from said third opening;
a fifth step of etching said floating gate film exposed from said first opening and said gate insulation film under said floating gate film, and etching said semiconductor substrate exposed from said third opening simultaneously, until said semiconductor substrate is exposed from said first opening;
a sixth step of simultaneously etching said semiconductor substrate exposed respectively from said first opening and said third opening; and
a seventh step of removing said etching mask and then filling respective trenches formed by said sixth step of etching with an insulating material.
In accordance with a third aspect of the present invention, there is provided a method for producing a non-volatile semiconductor memory device having a memory cell region, a peripheral circuit region, and a device isolating region on a semiconductor substrate, said memory cell region having a plurality of memory cells each comprising a floating-gate transistor, said peripheral circuit region including at least a transistor circuit in a periphery of said memory cell region, said device isolating region for isolating devices on said memory cell region from devices on said peripheral circuit region, said method comprising:
a first step of forming a field insulating film on said device isolating region and then forming a gate insulation film on said memory cell region and said peripheral circuit region;
a second step of forming a floating gate film on said gate insulation film and then selectively etching said floating gate film on said peripheral circuit region;
a third step of forming an etching mask having at least a first opening, a second opening, and a third opening, said first opening being provided to expose a part of said floating gate film on said memory cell region, said second opening being provided to expose a part of said gate insulation film on said peripheral circuit region, said third opening being provided to expose a part of said field insulating film on said device isolating region;
a fourth step of selectively etching said gate insulation film exposed from said second opening and said field insulating film exposed from said third opening until said semiconductor substrate is exposed from said second opening and said third opening;
a fifth step of etching said floating gate film exposed from said first opening and said gate insulation film under said floating gate film, and etching said semiconductor substrate exposed from said second opening and said third opening simultaneously, until said semiconductor substrate is exposed from said first opening;
a sixth step of simultaneously etching said semiconductor substrate respectively exposed from said first opening, said second opening, and said third opening; and
a seventh step of removing said etching mask and then filling respective trenches formed by said sixth step of etching with an insulating material.
In the method for producing a non-volatile semiconductor memory device, in accordance with the present invention, in the fifth step, it is preferable that, after simultaneously etching the floating gate film exposed from the first openings and the semiconductor substrate exposed from the second opening or the third opening until the gate insulation film is exposed from the first openings, the gate insulation film exposed from the first openings is selectively etched until the semiconductor substrate is exposed from the first openings.
In addition, in accordance with the present invention, it is preferable that the method for producing a non-volatile semiconductor memory device further comprises after the seventh step:
the eighth step of forming a well in the semiconductor substrate in the peripheral circuit region.
Further, in the method for producing a non-volatile semiconductor memory device, in accordance with the present invention, it is preferable that a trench formed in the peripheral circuit region is deeper than trenches formed in the memory cell region.
Still further, in the method for producing a non-volatile semiconductor memory device, in accordance with the present invention, it is preferable that the trench formed in the peripheral circuit region is deeper than a well formed in the peripheral circuit region.
In the method for producing a non-volatile semiconductor memory device, in accordance with the present invention, it is preferable that the trenches formed in the memory cell region isolate floating gates of the respective memory cells.
In the method for producing a non-volatile semiconductor memory device, in accordance with the present invention, it is preferable that the trench formed in the peripheral circuit region is formed in a source/drain region between adjacent transistors.
In the method of manufacturing a non-volatile semiconductor memory device, in accordance with the present invention, it is preferable that the etching mask is a photoresist.
In the method of manufacturing a non-volatile semiconductor memory device, in accordance with the present invention, it is preferable that the etching mask is a CMP stopper.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.